1. Field of the Invention
This invention relates to, for example, NAND flash EEPROM, and more particularly to a semiconductor memory device capable of storing multivalued data in a single memory cell.
2. Description of the Related Art
In a NAND flash memory, all of or half of a plurality of cells arranged in the row direction are connected to bit lines in a one-to-one correspondence. A write and read latch circuit is connected to each bit line. Data is simultaneously written into or read from all of or half of the cells arranged in the row direction. With the recent trend toward larger memory capacity, a multivalued memory which stores 2 bits or more of data in a cell has been developed (for example, Jpn. Pat. Appln. KOKAI Publication No. 2004-192789). In the multivalued memory, to store 2 bits in a cell, 4 threshold voltages have to be set in the memory cell. To store 3 bits in the memory cell, 8 threshold voltages have to be set in the cell. To store 4 bits in the memory cell, 16 threshold voltages have to be set in the cell.
As described above, when a plurality of bits of data is stored in a memory cell, a data storage circuit has to be connected to the bit line to store write data or read-out data. The data storage circuit is composed of a plurality of latch circuits.
As the number of threshold voltages stored in a single memory cell increases, the number of latch circuits constituting the data storage circuit increases, causing the problem of decreasing the writing speed. Accordingly, a semiconductor memory device capable of storing multivalued data, while suppressing the increase of latch circuits, and of high-speed writing has been desired.